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dsPIC30F6010A


High-Performance Modified RISC CPU
:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• 83 base instructions with flexible addressing modes
• 24-bit wide instructions, 16-bit wide data path
• 12 Kbytes on-chip Flash program space
• 512 bytes on-chip data RAM
• 1 Kbyte nonvolatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPs operation:
   - DC to 40 MHz external clock input
   - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)
• 27 interrupt sources
• Three external interrupt sources
• 8 user-selectable priority levels for each interrupt
• 4 processor exceptions and software traps
DSP Engine Features:
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/integer multiplier
• Single-cycle Multiply-Accumulate (MAC) operation
• 40-stage Barrel Shifter
• Dual data fetch
Motor Control PWM Module Features:
• 6 PWM output channels
   - Complementary or Independent Output modes
   - Edge and Center-Aligned modes
• 4 duty cycle generators
• Dedicated time base with 4 modes
• Programmable output polarity
• Dead-time control for Complementary mode
• Manual output control
• Trigger for synchronized A/D conversions
Quadrature Encoder Interface Module Features:
• Phase A, Phase B and Index Pulse input
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Interrupt on position counter rollover/underflow
Analog Features:
• 10-bit Analog-to-Digital Converter (ADC) with:
   - 1 Msps (for 10-bit A/D) conversion rate
   - Six input channels
   - Conversion available during Sleep and Idle
• Programmable Brown-out Reset