dsPIC30F6010

High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture with flexible Addressing modes
• 84 base instructions
• 24-bit wide instructions, 16-bit wide data path
• 144 Kbytes on-chip Flash program space (Instruction words)
• 8 Kbytes of on-chip data RAM
• 4 Kbytes of non-volatile data EEPROM
• Up to 30 MIPs operation:
   - DC to 40 MHz external clock input
   - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)
• 44 interrupt sources
   - 5 external interrupt sources
   - 8 user selectable priority levels for each interrupt source
   - 4 processor trap sources
• 16 x 16-bit working register array
DSP Engine Features:
• Dual data fetch
• Accumulator write back for DSP operations
• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single cycle hardware fractional/integer multiplier
• All DSP instructions single cycle
• ± 16-bit single cycle shift
Motor Control PWM Module Features:
• 8 PWM output channels
   - Complementary or Independent Output modes
   - Edge and Center Aligned modes
• 4 duty cycle generators
• Dedicated time base
• Programmable output polarity
• Dead Time control for Complementary mode
• Manual output control
• Trigger for A/D conversions
Quadrature Encoder Interface Module Features:
• Phase A, Phase B and Index Pulse input
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Interrupt on position counter rollover/underflow